1. Field of the Invention
The present invention relates to a method for the integration of two bipolar transistors in a semiconductor body, a semiconductor arrangement in a semiconductor body, and a cascode circuit.
2. Description of the Background Art
EP 0 493 854, which corresponds to U.S. Pat. No. 5,376,821, discloses vertically integrated cascode structures with two transistors for high-voltage applications. Here, a geometrically underlying transistor with a high blocking capability is vertically integrated with a geometrically overlying transistor. Arrangements of this type are employed preferably within the voltage range above 100V. The emitter region of the geometrically underlying transistor has, with the same conductivity type, a considerably higher dopant concentration than an adjacent collector drift zone of the geometrically overlying transistor. This increases the emitter effectiveness in particular of the geometrically underlying transistor. The vertical integration, for example, of two npn transistors produces a parasitic pnp transistor, so that the arrangement from EP 0 493 854 tends towards thyristor-like behavior and the collector current can be controlled only with limitations.
In EP 605 920, the tendency of the arrangement from EP 0 493 854 to thyristor-like behavior is reduced by increasing the Gummel number GB of the parasitic transistor. For this purpose, the emitter region of the bottom transistor is made as a highly doped layer, which continuously separates the base of the bottom transistor from the collector drift zone of the top transistor by producing a MESA (Table Mountain) structure. In EP 605 920, two transistors exclusively can be integrated into the MESA structure. In another embodiment, in EP 605 920 p-doped SiGe is used as an etching stop for the manufacture of the MESA structure in the base of the bottom transistor.